The present invention relates to testing analog driver circuitry using digital scan-based test methodologies such as level-sensitive scan design (LSSD) or any flip-flop based scan technique. Digital scan-based test methodologies typically define a number of Shift Register Latches (“SRLs”) that are electrically coupled in series and may be set deterministically by digital test equipment, such that application of a test vector defines the state of the device under test. Separate SRLs may be driven by outputs of the device under test. After the test is complete, the test equipment scans the output vector out of the SRLs and compares it against an expected output vector. SRLs which sense the output of a circuit under test can only interpret digital states and cannot interpret an analog state. Digital scan-based testing methodologies are well known in the art, and in particular, the implementation of a digital scan architecture into a design, the generation of patterns for testing the design, and the stimulation and observation of circuits within the design is well known. For example, see U.S. Pat. No. 4,298,980, entitled LSI Circuitry conforming to level sensitive scan design (LSSD) rules and method of testing same, by Hajdu et al. Use of SRLs for scan-based testing is well known to those skilled in the art. For example, see Miron Abramovici et al., “Digital Systems Testing and Testable Design”, IEEE PRESS, Ch. 9.3-9.9, 1990.
Analog driver circuitry typically requires functional testing to ascertain whether the driver functions as expected. As technology integration has become more complex, for example the integration of analog and digital circuits in the same design, testing of analog circuitry has become more difficult and expensive. There are several disadvantages associated with functional testing, such as: (1) it is more difficult to debug a functional test of a large analog/digital circuit as compared to digital scan-based logical paths; (2) it is more expensive to package a device for functional test than to test the device at the wafer level; and (3) more generally, development cost, difficult debugging and the high cost of test hardware make functional testing unappealing. For example, as operating voltages continue to decrease (e.g. 1.2V and below) and as the precision of digital-to-analog converters (DACs) increase, it is extremely difficult to digitally test the least significant bits (LSBs) of DACs where the DAC current output is converted to a voltage with a very low impedance (e.g. 50 ohms). For illustrative purposes, consider a seven-bit DAC which is operated at 1.2V. The output differential amplitude of the DAC for the LSB would be 9 mV at an output termination impedance of 50 ohms (1.2V/127). The offset voltage of a differential receiver is typically much larger than the LSB of the DAC, thus making the receiver's interpretation of the driver output unreliable. It is therefore desirable to provide a system and apparatus which is capable of testing an analog driver circuit of a mixed-signal design at the wafer-level, avoiding the extra cost associated with analog test equipment or on-chip analog BIST circuits.
See the following US patents for examples of analog test equipment, which are typically expensive and add to circuit test time: U.S. Pat. No. 5,610,530, entitled Analog interconnect testing, by Whetsel; U.S. Pat. No. 5,481,471, entitled Mixed signal integrated circuit architecture and test methodology, by Naglestad et al.; U.S. Pat. No. 5,107,208, entitled System for partitioning and testing submodule circuits of an integrated circuit, by Lee; and U.S. Pat. No. 6,011,387, entitled Analog autonomous test bus framework for testing integrated circuits on a printed circuit board, by Lee. See the following references for examples of analog BIST circuits implemented on chip, which are expensive in design time and chip area: U.S. Pat. No. 5,861,774, entitled Apparatus and method for automated testing of a programmable analog gain stage, by Blumenthal; and Karim Arabi, Bozena Kaminska, and Janusz Rzeszut, “BIST for D/A and A/D converters,” IEEE Design & Test of Computers v. 13 n. 4 Winter 1996, pp. 40-49.